This past year, the Hillsboro Herald covered a dozen stories on the exciting yet controversial expansion of the Urban Growth Boundary outside of Hillsboro, Oregon. As Data Centers and tech-related buildings continue their march West across the historic Tualatin Plains, tensions have risen with farmland preservation groups and locals caught in the path. Land speculators have moved into the fray, taking up options and purchase agreements and looking to cash in. The City of Hillsboro, seeking to expand the area’s Industrial land base, has been actively buying property and preparing infrastructure. As all that has played out, Governor Kotek’s office has been frantically pursuing the US CHIPS ACT and the billions of dollars of grant money available to create semiconductor jobs and expand research. Those jobs, mainly created by Intel in the modern era, power the State of Oregon’s economy and are at risk of going away.
Two forces are at play in the last two weeks of 2024 that will determine our futures: Oregon Senate Bill 4 and the US CHIPS ACT.
Even as Intel, the mighty computer giant, stumbles and sputters, Oregon and the people of greater Hillsboro find themselves at a Y in the road. That Y has one path in which Governor Kotek will use Senate Bill 4 (force #1) and her superpower to instantly add 373 or more acres to the Urban Reserve and Hillsboro’s Industrial land base. A move that would set up Hillsboro and Washington County for a decade or more of industrial growth. The other path would have Kotek not expanding the UGB and leaving, for now, Hillsboro to complete the North Hillsboro Industrial Park over the next 5 to 10 years on its current trajectory. Well over 500 acres of land is still available to build out, with tens of thousands of jobs already in place. Under SB 4, Kork has until the year’s end to decide.
The second force at play is the US CHIPS ACT and the significant investment that could still come from it. As Biden and his team prepare to relinquish the White House to the Trump Team, one final CHIPS ACT decision is akin to a lottery win. The Chips Act for America R&D Research facility, known as the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility, has not been awarded yet. That Multi-billion dollar facility is the jackpot that Oregon is hoping for. Senator Wyden and other key Oregon leaders continue to push for Oregon (Hillsboro) to land this project. As Intel lays off thousands and seems to be falling apart, getting this facility in the Hillsboro Tech cluster would steady the ship. Two weeks are left really in the decision making process, and everyone is leaving for the Holidays.
Two weeks left for Oregon and Hillsboro’s future to be decided. A decision is pending. One that will change our world here in Oregon.
Hillsboro is busy with demolition, sewer, and water plans at Sewell and Meek Roads, with houses coming down this week. Is that a sign that bug news is at hand? Maybe.
The NSTC will decide any day now on the last big award and has been quiet- but time is running out.
The Herald has asked Governor Kotek, Vince Porter, and her Press Staff what she will do. No answers yet.
What does the smartest AI in the World have to say: The Herald rarely uses AI. In this case, it would be impossible to complete the research on where the big commitment will land. So here is Gemni’s new deep dive engine response, which took it 12 minutes to complete. This is an AI response, but very compelling with sources provided:
QUESTION: Gemini, where is the US Government most likely to commit the last Chips Act for America R&D Research facility known as the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility?
ANSWER:
Predicting the Location of the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility
The CHIPS for America Act has spurred significant activity in the U.S. semiconductor industry, aiming to bolster domestic research, development, and manufacturing. A key component of this initiative is the establishment of the National Semiconductor Technology Center (NSTC), with three major facilities planned: the NSTC EUV Center in Albany, New York 1, the NSTC Administrative and Design Facility in Sunnyvale, California 1, and the forthcoming NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility 2. This report delves into the potential location of this final facility, analyzing the site selection criteria and the current landscape of the U.S. semiconductor ecosystem.
Timeline for NSTC Facilities
The three NSTC facilities are expected to become operational on different timelines. The NSTC Administrative and Design Facility is projected to be operational in 2025, followed by the NSTC EUV Center in 2026. The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility is expected to be operational in 20283.
Existing CHIPS Act R&D Facilities
The CHIPS Act has led to the establishment of various R&D facilities across the United States. These facilities focus on different aspects of semiconductor technology, including microelectronics commons, metrology, and workforce development programs. Some notable locations include:
- Albany, New York: Home to the NSTC EUV Center, focusing on extreme ultraviolet lithography research1.
- Sunnyvale, California: Anticipated location for the NSTC Administrative and Design Facility, which will serve as the administrative headquarters and have a heightened focus on the semiconductor design ecosystem. This includes access to semiconductor design, electronic design automation (EDA), and semiconductor workforce expertise, as well as administrative and corporate talent. Proximity to universities with advanced microelectronics research is also essential4.
- Various locations across the country: Numerous projects funded under the Microelectronics Commons, Metrology, and other initiatives, with awardees in states like California, Massachusetts, North Carolina, and Ohio6.
These existing and planned facilities provide a foundation for the NSTC and demonstrate the geographical diversity of CHIPS Act investments.
Criteria for Selecting CHIPS Act R&D Facility Locations
The selection process for CHIPS Act R&D facilities involves a comprehensive evaluation of various factors. These factors ensure the chosen locations have the necessary infrastructure, expertise, and resources to support advanced semiconductor research and development. The Department of Commerce and Natcast will manage the process, with support from a site selection firm that brings significant commercial experience in selecting facilities, including in the semiconductor industry4. Economic Development Organizations (EDOs) in each state and territory play a crucial role in this process, as they must complete an “Ecosystem Questionnaire” to be considered for the facility4. Key criteria include:
- Industry presence: A strong semiconductor ecosystem with existing companies, suppliers, and a skilled workforce. This includes the presence and planned growth of the semiconductor value chain, such as commercial semiconductor fabrication plants, advanced semiconductor packaging facilities, semiconductor equipment and material suppliers, and semiconductor design companies7.
- Workforce capabilities: Availability of skilled workers in semiconductor design, manufacturing, and related fields. This includes the number of people currently working in these areas and the types of expertise they possess7.
- Education and research: Presence of universities and research institutions with expertise in microelectronics. This encompasses the number and caliber of university research and advanced degree programs focused on microelectronics7.
- Workforce development: Strong training programs and initiatives to develop a skilled semiconductor workforce. This includes the number and quality of semiconductor-focused training programs7.
- Investment: A history of private and public investments in the semiconductor industry in the previous decade7.
- State and territory support: Supportive policies, incentives, and initiatives from state and local governments that benefit the semiconductor industry7.
- Financial sustainability: The facility must be financially sustainable by creating enduring value for decades and attracting investment from all types and sizes of companies9.
- 300mm capabilities: The facility needs to provide 300mm research, prototyping, and packaging capabilities3.
These criteria highlight the importance of a collaborative environment where industry, academia, and government work together to advance semiconductor technology.
Regions with Strong Semiconductor Industries and Research Capabilities
Several regions in the United States have emerged as hubs for semiconductor industries and research. These regions possess a combination of factors that make them attractive locations for the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility. Some prominent regions include:
- California: Home to Silicon Valley, California boasts a high concentration of semiconductor companies, a skilled workforce, and leading research institutions like Stanford University and the University of California, Berkeley10. This aligns with the criteria of industry presence, workforce capabilities, and education and research.
- Arizona: With a growing semiconductor industry and favorable operating costs, Arizona has attracted significant investments from major companies like Intel and TSMC12. The state also offers tax incentives and subsidies to encourage businesses, which aligns with the state and territory support criterion10.
- Texas: Texas has a business-friendly environment and has seen substantial investment in semiconductor manufacturing, with companies like Texas Instruments and Samsung establishing a presence12. This aligns with the industry presence and investment criteria.
- Oregon: The “Silicon Forest” in Oregon has a significant semiconductor workforce and is home to major companies like Intel13. This aligns with the industry presence and workforce capabilities criteria.
- New York: With the presence of the Albany NanoTech Complex and a growing semiconductor ecosystem, New York is becoming a key player in semiconductor research and development14. This aligns with the industry presence and education and research criteria.
These regions offer a combination of industry expertise, research capabilities, and supportive environments that could support the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility10.
National Advanced Packaging Manufacturing Program (NAPMP)
The National Advanced Packaging Manufacturing Program (NAPMP) is a critical component of the CHIPS Act, focusing on advancing semiconductor packaging technologies. The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility will play a key role in this program by providing researchers with prototyping, packaging, and research capabilities3. The NAPMP aims to stand up four baseline processes at the facility and has identified five key technology areas: heterogeneous integration, high-density substrates, advanced materials, testing, and security15.
Recent News and Announcements
Recent announcements and developments provide further insights into the potential location of the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility:
- Selection process: The Department of Commerce and Natcast have launched a multi-phase site selection process, involving an “Ecosystem Questionnaire” to identify suitable semiconductor ecosystems4.
- Focus on advanced packaging: The facility will provide prototyping, packaging, and research capabilities to support advanced packaging and semiconductor research3.
- Timeline: The facility is expected to be operational in 20283.
These updates suggest that the selection process is underway, with a focus on regions with strong advanced packaging capabilities and a thriving semiconductor ecosystem.
Speculation on the Most Likely Location
Based on the available information, several locations emerge as potential candidates for the NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility:
Arizona
Arizona’s strong semiconductor industry presence, favorable operating costs, and state-level incentives make it a strong contender. The state has attracted significant investment in recent years and has a growing ecosystem to support advanced packaging research and development12. The dry climate in Arizona is also beneficial for semiconductor manufacturing, reducing humidity-associated risks10.
California
California’s Silicon Valley remains a dominant force in the semiconductor industry, with a large talent pool, established infrastructure, and leading research institutions10. The state’s proximity to existing CHIPS Act facilities could also be advantageous10. However, the high cost of living and operating in California could be a potential drawback.
Texas
Texas has a business-friendly environment and has seen substantial growth in semiconductor manufacturing12. The state’s focus on attracting investment and developing its semiconductor workforce could make it an attractive location12. However, the limited presence of major research universities focused on semiconductor technology compared to California or New York could be a disadvantage.
Oregon
Oregon’s “Silicon Forest” has a long history in semiconductor manufacturing and a skilled workforce13. The state’s focus on innovation and its existing semiconductor ecosystem could make it a suitable location13. However, the concentration of semiconductor activity around Intel might limit the diversity of the ecosystem compared to other regions.
The co-location of NSTC research and NAPMP packaging capabilities in a single facility will provide the domestic semiconductor ecosystem with unique value to conduct collaborative semiconductor and advanced packaging research16. This factor could influence the site selection process, favoring locations with existing infrastructure and a collaborative environment.
To better understand the relative strengths and weaknesses of each potential location, the following table provides a summary based on the key criteria:
| Location | Industry Presence | Workforce Capabilities | Education & Research | Workforce Development | Investment | State/Territory Support | Overall Suitability |
|---|---|---|---|---|---|---|---|
| Arizona | Strong, growing industry with major companies like Intel and TSMC 12 | Growing workforce with skilled professionals 12 | Presence of universities with relevant programs, but not as extensive as California or New York | Initiatives to develop a skilled workforce, including tax incentives and subsidies 10 | Significant investment in recent years, including state incentives 12 | Supportive policies and incentives to attract businesses 10 | High |
| California | Dominant industry presence with Silicon Valley and a large talent pool 10 | Highly skilled and experienced workforce 10 | Leading research universities and institutions with extensive expertise 10 | Established workforce development programs and initiatives | High levels of investment, both public and private | Supportive policies, but high operating costs could be a factor | High |
| Texas | Growing industry with major companies like Texas Instruments and Samsung 12 | Skilled workforce, but potentially less specialized than other regions | Fewer top-tier research universities focused on semiconductors compared to other regions | Initiatives to attract investment and develop the workforce 12 | Substantial investment in manufacturing, with state incentives | Business-friendly environment with focus on attracting investment | Medium |
| Oregon | Established industry presence with a focus on manufacturing, primarily Intel 13 | Skilled workforce with experience in semiconductor manufacturing 13 | Some research institutions, but less prominent than other regions | Ongoing workforce development efforts | Significant investment from Intel, but less diverse than other regions | Supportive environment for innovation | Medium |
Conclusion
The NSTC Prototyping and NAPMP Advanced Packaging Piloting Facility represents a crucial investment in the future of the U.S. semiconductor industry. Its location will play a significant role in shaping the development of advanced packaging technologies and strengthening the domestic semiconductor ecosystem. While several regions have strong potential, the final decision will depend on a thorough assessment of various factors, including industry presence, workforce capabilities, research infrastructure, and state support. Based on the analysis, Arizona appears to be a strong contender due to its combination of a growing semiconductor industry, favorable operating costs, state-level incentives, and a supportive environment for research and development. However, California remains a significant competitor with its dominant industry presence, highly skilled workforce, and leading research institutions. The chosen location will become a hub for innovation, collaboration, and technological advancement in the semiconductor industry.
Works cited
- DoC, Natcast Announce First 2 CHIPS for America R&D Flagship Facilities – MeriTalk, accessed December 19, 2024, https://www.meritalk.com/articles/doc-natcast-announce-first-2-chips-for-america-rd-flagship-facilities/
- SCHUMER: THIS IS IT! AFTER YEARS OF ADVOCACY, ALBANY NANOTECH SELECTED AS AMERICA’S FIRST NATIONAL SEMICONDUCTOR TECHNOLOGY CENTER – CREATED BY HIS CHIPS & SCIENCE LAW | U.S. Senator Chuck Schumer of New York, accessed December 19, 2024, https://www.schumer.senate.gov/newsroom/press-releases/schumer-this-is-it-after-years-of-advocacy-albany-nanotech-selected-as-americas-first-national-semiconductor-technology-center_-created-by-his-chips-and-science-law
- Commerce Department, Natcast Launch Selection Processes for 3 CHIPS for America R&D Facilities – ExecutiveGov, accessed December 19, 2024, https://executivegov.com/2024/07/commerce-department-natcast-launch-selection-processes-for-3-chips-for-america-randd-facilities/
- www.nist.gov, accessed December 19, 2024, https://www.nist.gov/document/chips-america-and-natcast-processes-select-three-rd-facilities
- CHIPS for America R&D Facilities – Natcast, accessed December 19, 2024, https://natcast.org/facilities
- CHIPS R&D Programs – Semiconductor Industry Association, accessed December 19, 2024, https://www.semiconductors.org/chips-rd-programs/
- Site selection process for first three CHIPS R&D facilities revealed …, accessed December 19, 2024, https://ssti.org/blog/site-selection-process-first-three-chips-rd-facilities-revealed-0
- U.S. Semiconductor Ecosystem Map, accessed December 19, 2024, https://www.semiconductors.org/ecosystem/
- CHIPS for America R&D Facilities Model – National Institute of Standards and Technology, accessed December 19, 2024, https://www.nist.gov/document/chips-america-research-and-development-facilities-model
- Semiconductor Stats: Top US States Leading the Charge – Lantek Corporation, accessed December 19, 2024, https://www.lantekcorp.com/post/semiconductor-stats-top-us-states-leading-the-charge
- Semiconductors Shape Our World & Our Region – REDI Cincinnati, accessed December 19, 2024, https://redicincinnati.com/semiconductors-shape-our-world-our-region/
- Where the CHIPS Act is Transforming the US Semiconductor Ecosystem, accessed December 19, 2024, https://camoinassociates.com/resources/chips-act-is-transforming-the-us-semiconductor-ecosystem/
- Top 5 Job Locations for Semiconductor Manufacturing – Principal Service Solutions, accessed December 19, 2024, https://www.psstechnical.com/2023/01/top-5-job-locations-for-semiconductor-manufacturing/
- Strengthening U.S. Microelectronics: Dept. of Commerce Announces CHIPS Act R&D Flagship Facilities in New York and California – Public Spend Forum, accessed December 19, 2024, https://www.publicspendforum.net/blogs/public-spend-forum-2-2-2/2024/11/04/strengthening-u-s-microelectronics-dept-of-commerce-announces-chips-act-rd-flagship-facilities-in-new-york-and-california/
- IFTLE 609: TSMC/Amkor U.S. Advanced Packaging Partnership; Reshoring at IMAPS 2024, accessed December 19, 2024, https://www.3dincites.com/2024/10/iftle-609-tsmc-amkor-u-s-advanced-packaging-partnership-reshoring-at-imaps-2024/
- Biden-Harris Administration Announces First CHIPS for America R&D Facilities and Selection Processes | NIST – National Institute of Standards and Technology, accessed December 19, 2024, https://www.nist.gov/news-events/news/2024/07/biden-harris-administration-announces-first-chips-america-rd-facilities-and
Other News For Intel and Others of note as 2024 ends:
Oregon: Citizens and others have been concerned for a long time about the dangers toxic chemicals in semiconductor plants pose to employees. Recently, four workers were hospitalized for hazardous material exposure at Intel’s Aloha campus.
Micron: The company will receive $6.165 billion from the federal government to expand its manufacturing of memory chips and create approximately 20,000 jobs. This magnifies the fact that the US Government sees Micron as a valuable partner in manufacturing chips and as an alternative US company to Intel.
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Kotek is a crook and should be recalled and jailed for accepting illegal campaign funds from FTX via Wyden’s office and the Oregon Democratic Party, all while amAG Rosenblum, a dem operatives, conveniently disregarded her duty and turned away from her elected role.
Biden, he’s just a dottering fool now, the lamest of lame ducks.
And Intel?
Great reason to sacrifice valuable WashCo land…not!
Dems have ruined Oregon through self serving corruption, corporate giveaways, and empty promises, all while electricity costs go up and quality of life goes down.
But hey, no more mean tweets…yet.
I hope Trump cracks down hard in Oregon and runs these crooks up the river without a bridge, er, paddle.
Tell me what you really think? Happy Holidays.
Seems like Oregon has pretty slim chances at landing the packaging center at this point. Would a federal government shutdown officially kill all chances and run out the clock on the governors decision timeline?
Merry Christmas to all!
Haha, there will be no coal in my stocking this year, the Dems outlawed it! ;-)
https://oregoncatalyst.com/68894-money-scandal-entraps-kotek-fagan-now-wyden.html
It’s over: https://www.bizjournals.com/portland/news/2024/12/27/kotek-abandons-land-for-chips.html